This invention relates to high speed transceiver circuitry, and more particularly to equalizer circuitry used in such transceivers. Although the term “transceiver” is frequently used herein, the invention is primarily applicable to receiver circuitry or the receiver portion of transceiver circuitry.
High speed transceivers such as those operating at data rates of 3 Gbps and above require complex input equalization schemes to operate effectively. Such equalizers might contain multiple stages used to build a complex transfer function and/or to provide limiting amplification support at the receiver front-end. Because of the increased complexity of equalizers, and because of ever-shrinking circuit fabrication technologies, equalization stages may introduce non-negligible offsets in the signals at their outputs. The offset in an equalizer output signal may result in a shift in the DC value of the output signal. The offset in the output signal may limit the effectiveness of the equalization circuitry by causing errors during the extraction of the data signal from the equalizer input signal. The offset in the output signal may be especially pronounced in circuits in which many equalization stages are connected in series, because the offset of the output signal may increase as the square root of the number of stages cascaded in series in the signal path.
In addition to being sensitive to output signal offset, the performance of high speed transceivers may be affected by a reduced data eye at higher data rates. This can result in detection failure in highly attenuated customer links. The performance of transceivers may further be affected by layout effects, which play an increasing role in deep submicron technology. This can affect the performance of receiver (RX) signal paths and clock data recovery (CDR) phase detectors, compounding offset effects.
Offset cancellation schemes providing apparatus for canceling offset via PLD control have been described in Shumarayev et al. U.S. patent application Ser. No. 11/245,581, filed Oct. 6, 2005, which is hereby incorporated by reference herein in its entirety. The present disclosure provides methods and systems for canceling, minimizing, or compensating for input signal offset using decision feedback equalization (DFE) circuitry included in many receiver equalizers. The present methods and systems rely on DFE circuitry commonly found in receiver equalizers for their functioning. The methods and systems presented herein advantageously provide additional capabilities for eliminating input offset.